Recently, adaptive voltage position (AVP) control has been widely used in DC-DC regulators. The basic principle of such AVP control is referred to FIG. 1, wherein the y-axis represents the output voltage VO, while the x-axis represents the output current IO. The mathematic relation of the output voltage VO and the output current IO is:VO=VSET−R*IO   (1)wherein the coefficient R represents the variation slope. Both VSET and R are constants.
According to equation (1), the output voltage VO decreases when load current is increased rapidly (such as from light load condition to heavy load condition, i.e. the output current IO is increased). As can be seen from FIG. 2, the output voltage VO is decreased to VMAX from VMIN. When load current is decreased rapidly (such as from heavy load condition to light load condition, i.e., the output current IO is decreased), the output voltage VO is increased to VMIN from VMAX. The variation range of the output voltage is (VMAX−VMIN), wherein VMAX and VMIN are respectively the output voltage VO's allowed positive and negative fluctuating values. However, as shown in the middle graph of FIG. 2, to those circuits without AVP control, the output voltage VO is firstly decreased to VMIN, and then back to V immediately when load current is increased rapidly at time t1. Similarly, VO is increased to VMAX, and then back to V immediately when load current is decreased rapidly at time t2. Thus the variation range of the output voltage of these circuits is 0.5*(VMAX−VMIN). However, the variation range of the output voltage of circuits with AVP control is twice than that without AVP control as shown in the bottom graph of FIG. 2. Furthermore, when load current is increased, the output voltage of circuits with AVP control is decreased accordingly, which reduces power loss.
Prior art adaptive voltage position control is shown in FIG. 3. As shown in FIG. 3, a circuit 50 includes a conventional buck circuit as its main circuit which comprises a switch S1, a switch S2, an inductor L, a capacitor C0, and a load RL. Circuit 50 further includes a control circuit which comprises a current sensing resistor RS which is coupled between the inductor L and the capacitor C0, feedback resistors R1 and R2 which are coupled to the load RL in parallel, a comparator U0, an operational transconductance amplifier (OTA) U1, a current source A, a PWM generator and a driver. The OTA U1 has its two input terminals receive the drop voltage of the current sensing resistor RS, and converts the voltage into corresponding current ISENSE which is sent to the first input terminal of the PWM generator.
Feedback resistors R1 and R2 constitute a voltage divider, which feeds back the output voltage to the inverting input terminal of the comparator U0 via the resistor R3. The comparator U0 receives a reference VREF at its non-inverting input terminal. Current (I=K*ISENSE) provided by the current source US is sent to the inverting input terminal of the comparator U0 and one terminal of the resistor R3, wherein K is a constant coefficient, while ISENSE is the output current of the OTA U1. The output terminal of the comparator U0 is coupled to one terminal of a compensation net Zf—the other terminal of the compensation net Zf is grounded. The output terminal of the comparator U0 is also coupled to the second input terminal of the PWM generator. The PWM generator has its third input terminal receive a CLK signal, while its output terminal is coupled to the input terminal of the driver. The two output terminals of the PWM generator are coupled to the gates of the switches S1 and S2, respectively.
The operation of the main circuit of circuit 50 is as the operation of the conventional buck circuit, which is not illustrated herein for brevity. The operation of the control circuit of circuit 50 is illustrated as follows.
Since the comparator U0 exhibits a high impedance, the current provided by the current source US flows to the resistor R3. According to the “virtual short” characteristic of the comparator U0, the voltage at its non-inverting input terminal is equal to that at its inverting input terminal, namely,
          ⁢                                                        V              O                        *                          R              2                                                          R              1                        +                          R              2                                      +                  I          *                      R            3                              =              V        REF              ,                  ⁢                  ⁢    thus    ,                  ⁢                  V        O            =            ⁢                                                  (                                                R                  1                                +                                  R                  2                                            )                        *                          (                                                V                  REF                                -                                  I                  *                                      R                    3                                                              )                                            R            2                          =                ⁢                                                            V                REF                            *                              (                                                      R                    1                                    +                                      R                    2                                                  )                                                    R              2                                -                                                                      R                  3                                *                                  (                                                            R                      1                                        +                                          R                      2                                                        )                                                            R                2                                      *            I                              wherein I=K*ISENSE. As a result,
                              V          O                =                ⁢                                                                              V                  REF                                *                                  (                                                            R                      1                                        +                                          R                      2                                                        )                                                            R                2                                      -                                                                                R                    3                                    *                                      (                                                                  R                        1                                            +                                              R                        2                                                              )                                                                    R                  2                                            *              I                                =                    ⁢                                                                      V                  REF                                *                                  (                                                            R                      1                                        +                                          R                      2                                                        )                                                            R                2                                      -                                                                                R                    3                                    *                                      (                                                                  R                        1                                            +                                              R                        2                                                              )                                                                    R                  2                                            *              K              *                              I                SENCE                                                                        (        2        )            
Since ISENSE is determined by the output current IO, equation (2) behaves as the same function of the output voltage VO and the output current IO as equation (1).
Therefore prior art circuit 50 realizes the AVP control. That is, when the load current of circuit 50 is increased rapidly from light load condition to heavy load condition, the drop voltage of the current sensing resistor RS is increased, which causes the output current ISENSE of the OTA U1 to be increased. Thus the output current I of the current source US is increased, which causes the output voltage of circuit 50 to be deceased according to equation (2). On the contrary, when the load current of circuit 50 is decreased rapidly from heavy load condition to light load condition, the drop voltage of the current sensing resistor RS is decreased, which causes the output current ISENSE of the OTA U1 to be decreased. Thus the output current I of the current source US is decreased, which causes the output voltage of circuit 50 to be increased according to equation (2). Therefore, circuit 50 realizes the advantages of the AVP control such as a wide variation range of the output voltage and low power loss.
However, prior art circuit 50 receives the output current which is fed back by the current sensing resistor RS through the OTA U1, which requires two additional pins. In addition, the current sensing resistor RS consumes power, which decreases the efficiency. Furthermore, circuit 50 needs a current source US reflecting the output current, which causes the internal circuit complicated.
As a result, there is a need to provide a regulator which realizes the AVP control with simple internal circuit and fewer pins.